(1) Field of the Invention
The present invention relates to a method for making metal capacitors for ultra large scale integration (ULSI), and more particularly relates to a method for making small metal capacitors with high capacitance per unit area, low contact resistance, and tight distribution across the substrate.
(2) Description of the Prior Art
Capacitors on semiconductor chips are used for various integrated circuit applications. For example, these on-chip capacitors can be used as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution. These capacitors also have applications in analog/logic circuits.
Typically these capacitors are integrated into the semiconductor circuit when the semiconductor devices are formed on the substrate using one or two doped patterned polysilicon layers used to make the field effect transistors (FETs) and/or bipolar transistor. Alternatively, the capacitors can be fabricated using the multilevels of metal (e.g., Al/Cu) also used to wire up the individual semiconductor devices.
Generally the capacitors can be integrated into the circuit with no or with few additional process steps. The capacitance C for the capacitor is given by the expression EQU C=eA/d
where e is the dielectric constant, A is the capacitor area, and d is the thickness of the capacitor dielectric layer between the two capacitor electrodes. However, when doped polysilicon layers are used for the capacitor electrodes, the voltage coefficient (delta C/delta V) of the capacitor can be high. That is because the capacitance C is also a function of the space charge layer in the semiconductor material, which is also voltage dependent.
One method of minimizing this voltage coefficient is to heavily dope the polysilicon layers as described in U.S. Pat. No. 5,631,188 to Chang. Chang also forms a silicide layer on the top surface of the capacitor top electrode to reduce the contact resistance and therefore reduce the RC time constant.
Another method is to incorporate a polycide layer in the capacitor bottom electrode to increase the electrical conductivity to minimize the space charge layer effect as described in U.S. Pat. No. 5,338,701 to Hsu and in U.S. Pat. No. 5,554,538 also to Hsu.
By far the best method of minimizing the voltage coefficient (delta C/delta V) is to use a high electrical conductivity material, such as metal, for forming the capacitor electrodes instead of polysilicon semiconducting layers. The conventional method, with no additional processing steps, uses the intermetal dielectric (IMD) layer as the capacitor dielectric layer. However, for deep submicrometer processes (&lt;0.35 um) the IMD layer is usually chemically/mechanically polished (CMP) back to provide a planar surface on which to pattern distortion-free photo-resist patterns and to avoid residue (stringers, rails, etc.) during directional plasma etching to form patterns. Also, the polishing back of a relatively thick oxide results in non-uniform oxide thickness that would result in a undesirable wide spread in capacitance values across the wafer. Further, to minimize the capacitance between the metal lines, the IMD layer must be sufficiently thick to minimize RC delays and cross talk. This is contrary to the capacitor requirements of a thin dielectric layer for high capacitance. One method of making a metal capacitor is described in U.S. Pat. No. 5,624,864 to Arita et al. The method includes two extra masking steps and additional processing steps to form platinum-titanium capacitor electrodes. The method also focuses on heat treatment to improve capacitor oxide reliability. A method for making wound capacitors with increased dielectric break-down voltages is described in U.S. Pat. No. 5,614,111 to Lavene. Another method for making metal capacitors (back end capacitors) with high unit capacitance is described in U.S. Pat. No. 5,571,746 to Pan in which the bottom electrode, composed of doped polysilicon, is formed in a trench in the IMD layer, and a thin capacitor dielectric layer of silicon oxide/silicon nitride/silicon oxide (ONO) or silicon oxide is deposited on the bottom electrode.
There is still a need in the semiconductor industry to form metal capacitors for deep submicrometer technologies having high unit capacitance with low voltage coefficients and low contact resistance.